1. Field of the Invention
The present invention relates generally to the field of electrostatic discharge (ESD) protection for high frequency applications.
2. Description of the Related Art
The input impedance of a MOSFET, and some other devices, is capacitive making it inclined to build electrostatic charges. Thus, even a small amount of static charge placed on a bonding pad connected to a gate, from something or someone external to the MOSFET chip, can accumulate on the input capacitive impedance and build up to become a large enough electric field to cause the gate oxide of the MOSFET to break down.
An electrostatic discharge (ESD) circuit, or device, is typically applied to input, output, and input/output pads of a semiconductor integrated circuit (IC), or other sensitive device, to protect internal circuitry from electrostatic discharge, both in the manufacturing process and post-manufacturing handling.
With reference to FIG. 1, a basic ESD circuit 11 for an input signal includes a pair of clamping 13 and 15 coupled between an input pad 17 and internal circuitry 19. The purpose of diodes 13 and 15 is to prevent accumulated charge, or an incoming signal, from rising above the positive supply voltage Vdd or falling below the ground voltage by more than one forward diode voltage drop. Diode 13 provides primary protection against positive transients, and diode 15 provides primary protection against negative surges.
Many variations on the basic ESD circuit 11 are known. Sometimes, an optional current-limiting resistor is added between input pad 17 and ESD circuit 11, and diode 15 is sometimes left out of an ESD circuit when used on an output pad. However, the use of an electrostatic-protection diode, such as diode 13 and/or 15, is typically a part of most ESD structures.
The diode of an ESD circuit structure can be relatively large due to its need to withstand very high voltages. Therefore, an ESD circuit adds substantially to the loading capacitance on a pad, and this has a detrimental effect on high frequency input/output signals. Although at low frequency this capacitive loading, which may be as much as 5 pF, has negligible effect on input/output signal integrity, as the operating frequency increases to 1 GHz and beyond, ESD capacitive loading becomes a non-negligible contributor to signal degradation. A simple solution might be to reduce the diffusion area of an ESD circuit structure, and thereby lower its capacitance. However, this approach tends to degrade the ESD protection level, which typically needs to be greater than 2000 V.
Further complicating the use of ESD protection circuits in high frequency applications is that it has been shown that the junction capacitance of a diode is related to the voltage applied across the diode. Thus, the capacitive loading of an ESD circuit will fluctuate as the voltage at the input pad fluctuates, such as from the application of a logic signal transition.
With reference to FIG. 2, a first approach toward reducing the ill-effects of capacitive loading from an ESD circuit attempts to reduce the varying capacitance resulting from voltage fluctuations at input pad 17. In the present example, a first isolating diode 21 is inserted between input pad 17 and clamping diode 13, and a second isolating diode 23 is inserted between input pad 17 and clamping diode 15.
As stated earlier, a diode's capacitive value varies with the voltage applied across it. Thus, the present example attempts to stabilize the capacitive load seen on input pad 17 by reducing the amount of voltage fluctuations experience across the isolating diodes 21 and 23. That is, by minimizing voltage fluctuations on VD1, the voltage across first isolating diode 21, fluctuations in the capacitance of diode 21 may be reduced. Similarly by minimizing fluctuations in VD2, the voltage across second isolating diode 23, the fluctuations in the capacitance of diode 23 are also reduced.
To achieve this, a first differential amplifier 25, transfers the voltage applied to the anode of diode 21 to the cathode of diode 21. In this way, the voltage across diode 21 remains relatively constant irrespective of voltage fluctuations at input pad 17, and thus the capacitance due to diode 21 is likewise maintained relatively constant. In the same manner, a second differential amplifier 27 transfers the voltage applied to the cathode of diode 23 to the anode of diode 23. Since clamping diodes 13 and 15 are separated from input pad 17 by isolating diodes 21 and 23, respectively, the effects of capacitive loading on input pad 17 due to diodes 13 and 15 are reduced.
The use of differential amplifiers, however, limits its use in high frequencies applications. Additionally, differential amplifiers 25 and 27 contribute to the overall circuit complexity and capacitive loading of the ESD protection circuit. This approach, furthermore, does not address the issue of reducing the capacitance of clamping diodes 13 and 15.